1. Field of the Invention
This invention relates to the simulation of an integrated circuit's operation prior to the manufacture of the circuit and, more particularly, to detecting floating nodes (or transistor gates) within a netlist of nodes representing the circuit.
2. Description of the Related Art
Integrated circuits are highly complex and must be tested during production to ensure high quality and reliability. One of many tests which may be performed is a test of the current drawn by the circuit while in a static mode. This test may be referred to as a static current test or IDDQ test. The IDDQ test entails applying a power supply to the circuit and putting the circuit into an IDDQ test mode state (e.g., by clocking selected inputs for a predetermined time period and then waiting for the circuit to settle into the desired state). Once the circuit is in the IDDQ test mode state, current readings are taken between the power supply and ground.
When integrated circuits are production tested, large IDDQ values are often indicative of process failures. This is particularly true for CMOS circuits which typically have very small IDDQ values. Thus IDDQ values are often used for quality screening to eliminate potentially unreliable parts before they are sold. However, the usefulness of IDDQ values for quality screening may be undermined when an integrated circuit has a large IDDQ value due to floating transistor gates that are part of the design, i.e., not due to a process failure. For this reason, it is advantageous to design an IDDQ test mode into the integrated circuit that properly disables all analog circuitry, dynamic logic, and other circuitry that might cause current to flow, e.g., transistors whose control terminals (or "gates") are not tied to a power supply or ground (i.e., "floating"). Note that control terminals holding a decayed capacitive charge and not coupled to any power supplies or ground are considered to be floating transistor gates.
However, when designing an IDDQ test mode it is no simple task to eliminate all floating transistor gates or guarantee that all such transistors will not provide a current path from VCC to ground (or VSS). This is in part due to the large number of transistors involved in modern integrated circuits and the independent or block-oriented nature of the design process. For these reasons, a method for easily detecting floating transistor gates at the design stage is needed.
One possible solution is software modeling. Most integrated circuits can be modeled in software. Various software languages and circuit simulation applications (e.g., SPICE and Star-SIM.TM.) currently exists for that purpose. Using these languages and applications, a list of nodes and components between nodes can be fashioned. These lists are often referred to as "netlists." Using a netlist, circuit simulation applications can be used to determine if the integrated circuit being designed will function according to specifications. If a failure is detected, the circuit design can be modified prior to embodying the circuit upon silicon. Modeling and simulating an integrated circuit in software advantageously minimizes the time and cost associated with producing a viable integrated circuit.
However, using software to identify with certainty which transistor gates or nodes, if any, are floating is difficult because of inherent limitations within the simulation software. For these reasons, a method for easily detecting floating nodes in a netlist is desired. Furthermore, it would also be desirable for the method to work regardless of whether the netlist represents an analog, digital, or mixed-signal integrated circuit.